The present invention relates to the electrochemical metal plating of integrated circuit wafers to form multilevel integrated circuit structures.
Today's semiconductor industry is beginning to adopt a manufacturing process called "damascene" for forming interconnect lines and vias for multi-layer metal structures that provide the "wiring" of an integrated circuit. The damascene technique involves etching a trench in a planar dielectric (insulator) layer and filling the trench with a metal such as aluminum, copper, or tungsten. A technique called "dual-damascene" adds etched vias for providing contact to the lower level as the damascene structure is filled. There are several different ways to manufacture the damascene structure in the dielectric layer as practiced in the art and described in "Making the Move to Dual Damascene Processing", Semiconductor International, August 1997 hereby incorporated by reference. When copper is used as the filling, typically a layer of another material is first deposited to line the trenches and vias to prevent the migration of the copper into the dielectric layer. This migration barrier can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroless deposition. In addition to the migration barrier, sometimes a seed layer of the plating metal and/or other metals are applied to serve as a good site for electroless or electrolytic plating.
The filling process can be accomplished by plasma deposition, sputtering, or electroless or electrolytic deposition onto a seed layer. To achieve good fill of the typical micron to sub-micron wide trenches and vias, extra metal is deposited in the process, such metal covering areas of the wafer above and outside the trenches and vias. After filling, the extra metal must be removed down to the dielectric surface while leaving the trenches and vias filled in a process called "planarization". Standard chemical mechanical planarization (CMP) can be used to provide a planarized surface and metal removal.
As an alternative to CMP, electrochemical etching (ECE), electrochemical polishing (ECP), electropolishing, or electrochemical planarization (ECP) has been used. For the purpose of this application, the terms "electrochemical polishing", "electropolishing", "planarizing" and "electrochemical planarization" will be used interchangeably as they are in literature. The end goal is to have a very flat and smooth surface, the small difference between the terms is that the polishing desires to have a very smooth surface, while planarization desires to flatten-out topology and produce a flat smooth surface. "Electrochemical etch", however, has a different purpose, that is to remove material, generally uniformly, without regard to surface flatness.
U.S. Pat. No. 5,096,550 Mayer et al., entitled "Method And Apparatus For Spatially Uniform Electropolishing And Electrolytic Etching" describes conventional electropolishing with the addition of a non-conducting chamber or cup with a hole between the anode and the cathode, the workpiece electrically attached to the anode and the cathode external to the cup and above the layer of the hole. This approach is said to minimize the flow of hydrogen bubbles to the anode workpiece surface. For semiconductor wafers, which are bulk non-conductors, it is necessary to attach the electrode (anode) directly to the metallized front surface of the wafer, thereby limiting wafer surface area that can be used for active devices.
U.S. Pat. No. 5,256,565 Bernhardt et al., entitled "Electrochemical Planarization" describes a multi-step process, teaches separate apparatus for each step, first forming trenches or vias in a dielectric layer on a semiconductor substrate, optionally followed by one or more metal seed layers, not disclosed as how to form them, followed by metal deposition using conventional electroplating or electroless plating, followed by electrochemical polishing to form substantially flat damascene structures, optionally stopping before the metallized surface becomes partially eroded away and following with ion beam milling to remove the rest of the top surface of the metal, leaving the metal in the trenches and vias.
U.S. Pat. No. 5,567,300 Datta et al., entitled "Electrochemical Metal Removal Technique For Planarization Of Surfaces" describes an electrochemical cell and a planarization method for planarization of multilayer copper interconnections in thin film modules. The electrochemical cell and method is described as providing planarization of the first electrode surface (the wafer) using a scanning parallel second electrode with an electrolytic solution combined with a resistive salt mixture, ejected through the scanning electrode surface through built in nozzles, along with the appropriate voltage supply. Again, for semiconductor wafers, which are bulk non-conductors, it is necessary to attach the electrode (anode) directly to the metallized front surface of the wafer, thereby limiting wafer surface area that can be used for active devices.
U.S. Pat. No. 5,344,539 Shinogi et al., entitled "Electrochemical Fine Processing Apparatus" describes an apparatus for electrochemically performing an adding processing and removing processing of a substance such as a metal or polymer in a solution in order to produce a structure having a high aspect ratio. The apparatus comprises a container for the electrolytic solution, a first potential between the adding electrode and the support to be plated, a second potential between a removing electrode and the support to be plated, the second potential being opposite to the first potential, and a potential means. Shinogi et al. teaches applying the two separate but opposite potentials at the same time, or by first applying the adding potential between the adding electrode and the support to be plated and then switching to the removing potential between the adding electrode and the support to be plated. Shinogi et al. is limiting in that there is a requirement for two concurrent potentials of opposite polarity, or a stepwise process whereby the addition potential is followed by the removal potential. Shinogi et al. is advantageous over the previously described U.S. Pat. Nos. 5,096,550, 5,256,565, and 5,567,300 previously described in that simultaneous addition and removal of material is possible with two separate applied potentials. However, if the Shinogi et al. apparatus were used for semiconductor wafers, which are bulk non-conductors, it would be necessary to attach a common electrode directly to the metallized front surface of the wafer, thereby limiting wafer surface area that can be used for active devices.
U.S. Pat. No. 5,531,874 Brophy et al., entitled "Electroetching Tool Using Localized Application Of Channelized Flow Of Electrolyte," U.S. Pat. No. 5,536,388 to Dinan et al., entitled"Vertical Electroetch Tool Nozzle And Method," U.S. Pat. No. 5,543,032 to Datta et al., entitled "Electroetching Method And Apparatus" and U.S. Pat. No. 5,486,282 Datta et al., entitled "Electroetching Process For Seed Layer Removal In Electrochemical Fabrication Of Wafers" all use a linear scanning method of localizing the electrochemical reaction and are optimized in slightly different ways from etching both sides of a workpiece, to vertical scanning, to a salt solution combined with an electrolyte, to a process for forming c4 bumps on a substrate, respectively. All of these methods require an electrode attachment to the metallized seed layer or metallized surface when the workpiece is a semiconductor wafer, thereby limiting wafer surface area that can be used for active devices.
U.S. Pat. No. 5,695,810 Dubin et al., entitled "Use Of Cobalt Tungsten Phosphide As A Barrier Material For Copper Metallization" describes a technique for electrolessly depositing a CoWP barrier material onto copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer. This patent teaches the formation of a damascene structure on a semiconductor wafer by a combination of electroless deposition and chemical mechanical polishing. Also, the patent teaches the formulation of a via structure also using electroless deposition. This patent also discloses separate co-pending patent applications entitled "Electroless Cu Deposition On A Barrier Layer By Cu Contact Displacement For ULSI Applications;" Ser. No. 08/587,262 filed Jan. 16, 1996; "Selective Electroless Copper Deposited Interconnect Plugs For ULSI Applications," Ser. No. 08/587,264; filed Jan. 16, 1996; and "Protected Encapsulation Of Catalytic Layer For Electroless Copper Interconnect," Ser. No. 08/587,264; filed Jan. 16, 1996. Electroless deposition as taught by Dubin et al. has some advantages in forming a damascene structure onto semiconductor wafers, but it may also have disadvantages, such as the quality of the adhesion of the barrier layer to the material being plated and possible undesirable contamination of the semiconductor due to the metal catalyst used to initiate the deposition of the barrier metal. The biggest concern in the Dubin et al. process is the inherent difficulty in controlling any electroless deposition process uniformity, as compared to an electroplating process, especially for the fine features present in semiconductor manufacturing.
What is needed is a method and apparatus for electrochemical metal plating of semiconductor wafers that does not require a physical electrical connection to the surface of the semiconductor wafer.